Introduction to Xilinx Tools

Using the Lab Machines

Welcome to the world of embedded systems. Today you will get an introduction to the Xilinx ISE software.  You will be implementing a simple embedded system to get you familiar to the tools.  To open Xilinx ISE on a lab machine, first login and open a terminal and type ise.

Using Xilinx ISE 13

This tutorial will help you become familiar with using Xilinx ISE 13 to develop on a Xilinx based FPGA board.

Step 1: Project Setup

• Open Xilinx ISE Design Suite 13



• Select a New Project...
  Note: If you are not prompted to create a new project, start the new project wizard by selecting New Project in the File menu.
  



• Enter the desired project folder name.
  (I.E. Tutorial)
  Enter the desired project folder location.
  (I.E. C:\Documents and Settings\Embedded Systems Lab\Desktop\)
  Enter a Description of the Project.
  Select Next >
  
  
  
• Select the Evaluation Development Board, if known.
  (I.E. Spartan-3E Starter Board)
  Otherwise, you will have to look at the FPGA physical board chip or product documentation for the Family, Device, Package, and Speed.
  
  Other settings are shown below.
  Synthesis Tool: XST (VHDL/Verilog)
  Simulator: ISim (VHDL/Verilog)
  Preferred Language: VHDL Property Specification in Project File: Store all Values
  Manual Compile Order: Unselected
  VHDL Source Analysis Standard: VHDL-93
  Enable Message Filtering: Unselected
  
  Select Next >
  
  
  
• A Project Summary will then be shown. Review the content for correctness and select Finish if correct, otherwise repeat the previous steps.
  

Step 2:  Entity Setup

• You are now viewing the Project Navigator. The Sources in the Project section will automatically organize your VHDL module tree (Top Left). The Processes for Source pane will allow you to perform various processes such as synthesis or device programming, view reports, and access useful tools (Middle Left). The bottom pane contains console output - notice the Console, Errors, Warnings tabs; these are useful in debugging (bottom section). The right are is used to display any files or documents you have opened.
  
  
  
• Now you will create a new VHDL entity.
  Right-Click on the chip icon and select New Source.
  Take note that you can add already created sources.
  
  
  
• Select VHDL Module
  Give the module a name.
  (I.E. Pass_thru)
  Select Next >
  
  
  
• The Entity name will near in its text box. The Architecture name can also be changed in its text box as well, for this example we are describing a Behavioral.
  In the first Port Name text box give the port a name button_north, since this is a single input it has no bus; do this for buttton_south, buton_west, and button_west. We will be using these for input signals so select "in" for the signal directions.
  In the fifth Port Name text box give it the name switches, since switches is group of multiple signals give these a bus by checking the bus box and select the "in" data direction. We have four switches on this particular board so select put "3" in MSB text box, this is because we count the signal 3, 2, 1, and 0.
  In the sixth Port Name text box give it the name leds, since switches is group of multiple signals give these a bus by checking the bus box and select the "out" data direction. We have eight LEDs on this particular board so select put "7" in MSB text box, this is because we count the signal 7, 6, 5, 4, 3, 2, 1, and 0.
  Select Next >
  
  
  
• Review the summary of the entity then Select Finish.

Step 3: Synthesis

• Enter the following code.
  

Once Entered, now we need to check if the VHDL syntax is correct. Expand the Synthesize - XST tree and double click Check Syntax.



• If correct, then close tree and select Synthesize - XST to check to make sure the code is synthesizable; there should not be warnings or errors.
  
  
  

Step 4: Testbench

• Add a new source.


• Select VHDL Test Bench
  File name: pass_thru_tb
  
• Select Next >




• Select pass_thru for the associate source.
  
• Select Next >




• Review the Summary and select Finish.
  
  


• Select the Simulation on the view button above the VHDL module tree to see the testbench and simulation tree.
  
  
  Enter the code.
  


• In the Processes for Source pane expand the ISim Simulator and double click the Behavioral Check Syntax. If correct then there will be no errors.
  
  


• In the Processes for Source pane double click the Simulate Behavior Model. A new window will appear showing the simulation. If the test bench completes with no errors in the command prompt then simulation was successful for the tested cases. You might have to zoom out to view the signals in ns. Zoom out by pressing F7 and zoom in by pressing F8 or use the shortcuts on the top bar. Note: the testbench does not necessarily run to the final wait statement. You might need to run the test until you get the message "Note: Done with testbench".
  
  
  
• You can also select the signals and change the display format from binary to hexadecimal by selecting radix hexadecimal. Other functionality includes: being able to add signals to the test bench from internal signals, by dragging signals/variables from the center pane to the right most pane. Other components can be explored by expanding and selecting object in the left most pane.
  
  
• Switch back to implementation view to continue editing.

• Repeat the processes above to add the full subtractor. Then select it as the top module to do syntax and synthesis. Switching modules is essential in testing components when adding modules.
  Enter the following code.
  
  


• Repeat the processes for the full subtractor testbench. Enter the following code.
  

• Repeat the processes above to add the generic subtractor. Then select it as the top module to do syntax and synthesis. Switching modules is essential in testing components when adding modules. Enter the following code.
  


• Repeat the processes for the generic subtractor testbench. Enter the following code.
  


• When the design has been fully tested in synthesis and simulation, then you proceed to the implementation to see the area and speed of your design.
  
  

• Templates are a very useful resource for engineers. Unlike many other programming languages, only a subset of VHDL can be synthesized to hardware implementation. To access the language templates: go to Edit > Language Templates.
  
  


• In viewing the template look only at VHDL > Synthesis Constructs > Coding Examples when design hardware. These templates will give you an intuition for how to create hardware structures.