Finite State Machine Schematic on Xilinx Vivado IDE Tool
This Include - Captured RTL Schematic of Intended FSM. Captured Timing diagram of Designed FSM. FSM in terms of input Clock, input M, P , Secondary State variable A,B and output Z.
Me concernant
Hi, I am currently working as a Research Scholar at DRDO Laboratory . I have post graduation in Microelectronics and VLSI Design. Skills - >> Digital Integrated Circuit >> Verilog HDL/ VHDL >> RTL Design >> SOC Verification using System Verilog >> FPGA Prototyping EDA Tool- >> Xilinx Vivado IDE Tool >> Xilinx ISE Design Suite >> Altera ModelSim Designed Digital Circuits- 1. Design, Verification and Implementation of an FPGA-based Monitoring System 2. Successive Approximation Register type Analogue-to-Digital Converter (ADC) System 3. Pulse Width Modulation (PWM) Motor Control 4. Memory Design (SRAM & DRAM) 5. First-In-First-Out Register (FIFO) 6. Serial Peripheral Interface(SPI) Thanks
