Published March 16, 2024

Dual Address Cosine ROM Using Verilog in Vivado

The Dual Address Cosine ROM works on Discrete Cosine Transform and Quantization for dual data transfer concurrently.

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Dual Address Cosine ROM Using Verilog in Vivado

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AMD Vivado Design Suite HLx Editions

Story

The Dual Address Data Read Only Memory helps in parallel transfer of data. For this, dual address and dual output of data are the main design constraints required. Furthermore, there also a need exists of clock in order to achieve synchronous pipelining (Fetch->Decode->Execute->Write). The number of bits in address bus (i.e. n) results the number of locations in ROM with the exponential of two i.e. 2^n and the data width is 64 bits. Hence, the ROM content the data of 8x64 bits in a unique architectural block.

In DCTQ implementation, the cosine transform coefficient from the block of data as well as cosine terms along its transpose is computed. For this, the value realization is done by using two separate address ROM in which one stores cosine (C) and the other stores its transpose (C^T). Since DCTQ requires both cosine and its transpose simultaneously for performing algorithm, we need dual data address rather than single address. Coming to the need of accuracy, the cosine and its transpose magnitude is made twice during storage and its coefficient is reduced by two, so that it can possess neutrality. Since the output data get delayed by two clock cycles, we also use two stage pipelining to match the pace so that the desired constraints can be achieved at the output.

Code

Verilog HDL Source Code

module COSINE_ROM (clk, addr1, addr2, dout1, dout2);
    input clk; 
    input [2:0]addr1; 
    input [2:0]addr2;
    output [63:0] dout1;   //64 bit data out
    output [63:0] dout2;   //64 bit data out
  
    reg [63:0] r1;
    reg [63:0] r2;
    reg [63:0] pr1;   // first pipeline register 
    reg [63:0] pr2;   // second pipeline register
    reg [63:0] dout1;
    reg [63:0] dout2;

    wire [63:0] loc0;   //declaration of ROM data as nets
    wire [63:0] loc1;
    wire [63:0] loc2;
    wire [63:0] loc3;
    wire [63:0] loc4;
    wire [63:0] loc5;
    wire [63:0] loc6;
    wire [63:0] loc7;
  
    assign loc0 = 64'hA3A3A3A3A3A3A3A3;     //ROM data of 8 numbers having 8 bit data per location
    assign loc1 = 64'hAE5388B3568ED75D;
    assign loc2 = 64'hB48A58E49B447C02;
    assign loc3 = 64'hA7329B2092E399DA;
    assign loc4 = 64'hD7852398C002B27A;
    assign loc5 = 64'hE821B5490C12398E;
    assign loc6 = 64'hE757B8CA809B19AE;
    assign loc7 = 64'h6A7B459D001A496D;

    always@(loc0 or loc1 or loc2 or loc3 or loc4 or loc5 or loc6 or loc7 or addr1 or addr2)
    begin
       case (addr1)            //addr1 serves as address to read data
         3'b000: r1 = loc0;
         3'b001: r1 = loc1;
         3'b010: r1 = loc2;
         3'b011: r1 = loc3;
         3'b100: r1 = loc4;
         3'b101: r1 = loc5;
         3'b110: r1 = loc6;
         3'b111: r1 = loc7;
         default: r1 = loc0;
       endcase
       case (addr2)            //addr2 serves as address to read data
         3'b000: r2 = loc0;
         3'b001: r2 = loc1;
         3'b010: r2 = loc2;
         3'b011: r2 = loc3;
         3'b100: r2 = loc4;
         3'b101: r2 = loc5;
         3'b110: r2 = loc6;
         3'b111: r2 = loc7;
         default: r2 = loc0;
         endcase
    end

    always@(posedge clk)  //first pipelining stage
    begin
        pr1 <= r1;
        pr2 <= r2;
    end

    always@(posedge clk)  //second pipelining stage
    begin
        dout1 <= pr1;
        dout2 <= pr2;
    end

endmodule

Credits

Yash Raj

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Dual Address Cosine ROM Using Verilog in Vivado

Things used in this project

Software apps and online services

Story

Schematics

Behavioral Simulation

RTL Schematic

RTL Dataflow

Synthesis Schematic

Synthesis Devices

Implementation Schematics

Implementation Devices

Code

Verilog HDL Source Code

Credits

Yash Raj

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Dual Address Cosine ROM Using Verilog in Vivado

Dual Address Cosine ROM Using Verilog in Vivado

Things used in this project

Software apps and online services

Story

Schematics

Behavioral Simulation

RTL Schematic

RTL Dataflow

Synthesis Schematic

Synthesis Devices

Implementation Schematics

Implementation Devices

Code

Verilog HDL Source Code

Credits

Yash Raj

Comments

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